The present invention relates to an improved low voltage swing logic circuit for use in an integrated circuit.
Low voltage swing ("LVS") circuits are known per se. Systems built upon such circuits typically carry data on a pair of wires. During a precharge phase, both the wires are precharged to a predetermined potential. During an evaluation phase, a first wire carries a true value of the data signal and a second wire carries the complement value of the data signal. The LVS circuit generates an output response to voltage differences between the true and complementary signals.
LVS circuits are advantageous because they achieve higher data throughput than conventional "full swing" logic circuit. In a "full swing" circuit, a data signal typically transitions completely to either ground or V.sub.CC before the circuit can generate an output signal. Because an LVS circuit can sense data from small voltage differences, LVS circuits realize faster operation and improved throughput than conventional full swing logic circuits. Further, because full swing transitions are not necessary to detect useful data, the voltages used within an LVS integrated circuit are reduced over a corresponding full swing circuit, thereby contributing to reduced power consumption.
Because each data signal is carried through the LVS circuit on a pair of wires, LVS circuits include twice as many metal tracks or wires between circuit elements than are in a corresponding full swing circuit. Although the metal pitch may be made tighter in an LVS circuit because of the reduced voltages, the doubling of wires in an LVS integrated circuit can lead to wiring congestion in the circuit. Such disadvantages can limit the applications for which circuit designers may choose to use LVS circuits.
Accordingly, there is a need in the art for an integrated circuit that possesses the speed and throughput advantages of LVS circuits but that also do not suffer the corresponding disadvantages of wiring congestion.